The present invention relates generally to methods and techniques for switching among input clocks in synchronous circuits, and more particularly relates to methods and techniques for switching among a plurality of input clocks with little or no phase change at the output.
It is a common requirement in the field of digital electronics to require the switching between two similar input clock sources. Often, the input clocks are switched with a simple multiplexer without regard to the phase difference of the input clocks. The resulting output clock can experience a sudden phase change or even a very short transient pulse. These anomalies, or glitches, can cause incorrect behavior when this switched clock is used as reference inputs to PLLs (Phased Locked Loops), DLLs (Digital Locked Loops) or as clock inputs to state machines or other synchronous logic as these systems often have requirements for minimum high and low periods or minimum phase change.
One possible example of this would be the case of a high speed serial interface. This interface may need to work off a local reference clock during the datastream clock detection and then switch to the clock recovered from the datastream once detection has completed. Normally the reference clock will be very similar in frequency from the recovered clock (of the order of maybe 100 parts per million), but, due to crystal clock source tolerances, will not be exactly the same. Switching without regard to the phase of the clocks can result in a glitch.
To prevent glitch occurrence, many clock switching techniques, for example U.S. Pat. Nos. 5,197,126 and 6,472,909, suppress one or more clock pulses on the switched output at the time of switching. This may be acceptable for some logic circuits but is often unacceptable if used as the reference input to a PLL or DLL as the resulting clock output of these devices will often be unpredictable, causing problems in state machines or other synchronous logic. For the purposes of these circuits, and this invention, suppression of a clock pulse is henceforth also considered a glitch.
There has therefore been a need for a method for switching among asynchronous input clocks in a synchronous circuit without glitches in the output.
The present invention allows the selection between two clocks of similar, but not identical, frequencies without producing glitches, that is to say transient pulses, sudden phase change or suppressed clock edges. In an exemplary arrangement, the invention uses registers to detect the relative phase of the clocks and only allows the switching to occur when the phase difference between the clocks does not exceed a maximum permissible phase difference. This, combined with register timing parameters, permits switching among the clocks with no glitches and very small phase change at the output. The output of this circuit can be used to drive PLLs and other electronic circuitry that is sensitive to clock glitches.
The invention relies on the two input clocks being at different frequencies, even if only slightly different, and allows a switch from one to the other when the two clocks are substantially in phase. Because of this the switching may not be instantaneous.